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19-2698; Rev 1; 5/04
2-Wire-Interfaced 8-Bit I/O Port Expander with Reset
General Description
The MAX7310 provides 8-bit parallel input/output port expansion for SMBusTM-compatible and I2CTM-compatible applications. The MAX7310 consists of an input port register, an output port register, a polarity inversion register, a configuration register, a bus timeout register, and an SMBus/I2C-compatible serial interface. The system master can invert the MAX7310 input data by writing to the active-high polarity inversion register. The system master can enable or disable bus timeout by writing to the bus timeout register. Any of the eight I/O ports may be configured as input or output. An active-low reset input sets the eight I/Os as inputs. Three address select pins configure one of 56 slave ID addresses. The MAX7310 is available in 16-pin thin QFN, TSSOP, and QSOP packages and is specified over the -40C to +125C automotive temperature range. 400kHz 2-Wire Interface 2.3V to 5.5V Operation Low Standby Current (1.7A typ) Bus Timeout for Lock-Up-Free Operation 56 Slave ID Addresses Polarity Inversion Eight I/O Pins that Default to Inputs on Power-Up 5V Tolerant Open-Drain Output on I/O0 4mm x 4mm, 0.8mm Thin QFN Package -40C to +125C Operation
Features
MAX7310
Applications
Servers RAID Systems Industrial Control Medical Equipment Instrumentation, Test Measurement
SMBus is a trademark of Intel Corp. Purchase of I2C components of Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
PART MAX7310AUE MAX7310AEE MAX7310ATE
Ordering Information
TEMP RANGE PINPACKAGE PKG CODE -- --
-40C to +125C 16 TSSOP -40C to +125C 16 QSOP
-40C to +125C 16 Thin QFN T1644-4
Pin Configurations
SDA V+ 14
TOP VIEW
SCL 1 SDA 2 AD0 3 AD1 4 AD2 5 I/O0 6 I/O1 7 GND 8 16 V+ 15 RESET 14 I/O7 13 I/O6 AD1 AD2 I/O0 2 3 4 AD0 1
16
15
SCL
13
RESET
12 I/O7 11 I/O6 10 I/O5 9 I/O4 8 I/O3
MAX7310
12 I/O5 11 I/O4 10 I/O3 9 I/O2
MAX7310
5 I/01
6 GND
7 I/O2
TSSOP/QSOP
THIN QFN
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
2-Wire-Interfaced 8-Bit I/O Port Expander with Reset MAX7310
ABSOLUTE MAXIMUM RATINGS
V+ to GND ................................................................-0.3V to +6V I/O1-I/O7 as an Input .......................(VSS - 0.3V) to (VDD + 0.3V) I/O0 as an Input..............................................(VSS - 0.3V) to +6V SCL, SDA, AD0, AD1, AD2, RESET ...............(VSS - 0.3V) to +6V DC Current on I/O0 ........................................................ +400A DC Current on I/O1 to I/O7 ............................................. 50mA Maximum GND and V+ Current........................................180mA Continuous Power Dissipation (TA = +70C) 16-Pin TSSOP (derate 5.7mW/C above +70C) .........457mW 16-Pin QSOP (derate 8.3mW/C above +70C)...........667mW 16-Pin Thin QFN (derate 16.9mW/C above +70C) ...1349mW Operating Temperature Range .........................-40C to +125C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V+ = 2.3V to 5.5V, GND = 0, RESET = V+, TA = -40C to +125C, unless otherwise noted. Typical values are at V+ = 3.3V, TA = +25C.) (Note 1)
PARAMETER Supply Voltage Supply Current SYMBOL V+ I+ All outputs floating, all inputs at V+ or GND, fSCL = 400kHz All outputs floating, all inputs at V+ or GND, fSCL = 0 V+ = 2.3V V+ = 3.3V V+ = 5.5V V+ = 2.3V V+ = 3.3V V+ = 5.5V CONDITIONS MIN 2.3 19 29 65 1.5 1.7 2.1 1.6 VIL VIH VOIL IL CI VIL VIH IL IOL All inputs at V+ or GND V+ = 2.3V, VOL = 0.5V Low-Level Output Current V+ = 3.3V, VOL = 0.5V V+ = 5.5V, VOL = 0.5V High Output Current for I/O1-I/O7 AD0, AD1, AD2, AND RESET Input Voltage Low Input Voltage High 2 0.8 V V IOH V+ = 3.3V, VOH = 2.4V V+ = 5.5V, VOH = 4.5V 2 -1 8 12.5 19 6.5 12.5 14 22 30 11 18 mA mA +1 ISINK = 6mA -1 10 0.8 2 0.4 +1 TYP MAX 5.5 30 40 80 3.4 3.9 5 2.1 0.8 V V V V A pF V V A A A UNITS V
Standby Current Power-On Reset Voltage SCL, SDA Input Voltage Low Input Voltage High Low-Level Output Voltage Leakage Current Input Capacitance I/Os Input Voltage Low Input Voltage High Input Leakage Current
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2-Wire-Interfaced 8-Bit I/O Port Expander with Reset
DC ELECTRICAL CHARACTERISTICS (continued)
(V+ = 2.3V to 5.5V, GND = 0, RESET = V+, TA = -40C to +125C, unless otherwise noted. Typical values are at V+ = 3.3V, TA = +25C.) (Note 1)
PARAMETER Leakage Current Input Capacitance SYMBOL CONDITIONS MIN -1 10 TYP MAX +1 UNITS A pF
MAX7310
AC ELECTRICAL CHARACTERISTICS
(V+ = 2.3V to 5.5V, GND = 0, RESET = V+, TA = -40C to +125C, unless otherwise noted.) (Note 1)
PARAMETER SCL Clock Frequency BUS Timeout Bus Free Time Between STOP and START Condition Hold Time (Repeated) START Condition Repeated START Condition Setup Time STOP Condition Setup Time Data Hold Time Data Setup Time SCL Low Period SCL High Period SCL/SDA Fall Time (Transmitting) Pulse Width of Spike Supressed PORT TIMING Output Data Valid Input Data Setup Time Input Data Hold Time RESET Reset Pulse Width 100 ns tPV tPS tPH Figure 9 Figure 10 Figure 10 29 0 1 s s s SYMBOL fSCL tTIMEOUT tBUF tHD, STA tSU, STA tSU, STO tHD, DAT tSU, DAT tLOW tHIGH tF tSP Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 (Note 3) Figure 2 Figure 2 Figure 2 Figure 2 (Note 4) (Note 5) 50 0.1 1.3 0.7 250 (Note 2) 30 1.3 0.6 0.6 0.6 0.9 CONDITIONS MIN TYP MAX 400 60 UNITS kHz ms s s s s s s s s ns ns
Note 1: All parameters are 100% production tested at TA = +25C. Specifications over temperature are guaranteed by design. Note 2: Minimum SCL clock frequency is limited by the MAX7310 bus timeout feature, which resets the serial bus interface if either SDA or SCL is held low for a 30ms minimum. Note 3: A master device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIL of the SCL signal) in order to bridge the undefined region of SCL's falling edge. Note 4: tF measured between 90% to 10% of V+. Note 5: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
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2-Wire-Interfaced 8-Bit I/O Port Expander with Reset MAX7310
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
MAX7310 toc01
STANDBY SUPPLY CURRENT vs. TEMPERATURE
MAX7310 toc02
SUPPLY CURRENT vs. SUPPLY VOLTAGE
fSCL = 440kHz, NO LOAD ON I/O0-I/O7
MAX7310 toc03
32 31 SUPPLY CURRENT (A) 30 29 28 27 26
V+ = 3.3V, fSCL = 440kHz, NO LOAD ON I/O0-I/O7
2.50 2.25 SUPPLY CURRENT (A) 2.00 1.75 1.50 1.25 1.00
V+ = 3.3V, fSCL = 0, NO LOAD ON I/O0-I/O7
70 60 SUPPLY CURRENT (A) 50 40 30 20 10
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
I/O0-I/O7 OUTPUT SINK CURRENT vs. TEMPERATURE
MAX7310 toc04
I/O0-I/O7 OUTPUT SINK CURRENT vs. SUPPLY VOLTAGE
MAX7310 toc05
I/O1-I/O7 OUTPUT SOURCE CURRENT vs. TEMPERATURE
V+ = 2.3V, VOH = 1.4V
MAX7310 toc06
30 25 VCC = 3.3V SINK CURRENT (mA) 20 15 10 5 VOL = 0.5V 0 VCC = 2.3V
35 30 SINK CURRENT (mA) 25 20 15 10 5 VOL = 0.5V 0
9
8 SOURCE CURRENT (mA)
7
6
5
4 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) SUPPLY VOLTAGE (V)
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
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2-Wire-Interfaced 8-Bit I/O Port Expander with Reset
Pin Description
PIN TSSOP/ QSOP 1 2 3 4 5 6 7 8 9-14 15 16 -- THIN QFN 15 16 1 2 3 4 5 6 7-12 13 14 PAD NAME SCL SDA AD0 AD1 AD2 I/O0 I/O1 GND I/O2-I/O7 RESET V+ Exposed pad Serial Clock Line Serial Data Line Address Input 0 Address Input 1 Address Input 2 Input/Output Port 0 (Open Drain) Input/Output Port 1 Supply Ground Input/Output Port 2--Input/Output Port 7 External Reset (Active Low). Pull RESET low to configure I/O pins as inputs. Set RESET high for normal operation. Supply Voltage. Bypass with a 0.047F capacitor to GND. Exposed Pad on Package Underside. Connect to GND. FUNCTION
MAX7310
AD0 AD1 AD2 SCL SDA INPUT FILTER SMBus CONTROL INPUT/ OUTPUT PORTS
MAX7310
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
8 BIT
WRITE PULSE N READ PULSE
V+ RESET POWER-ON RESET
GND
Figure 1. MAX7310 Block Diagram
Detailed Description
The MAX7310 general-purpose input/output (GPIO) peripheral provides up to eight I/O ports, controlled through an I 2 C-compatible serial interface. The MAX7310 consists of an input port register, an output
port register, a polarity inversion register, a configuration register, and a bus timeout register. An active-low reset input sets the eight I/O lines as inputs. Three slave ID address select pins (AD0, AD1, and AD2) choose one of 56 slave ID addresses (Figure 1).
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2-Wire-Interfaced 8-Bit I/O Port Expander with Reset MAX7310
Table 1 is the register address table. Tables 2-6 list register 0 through register 4 information. SCL is high. The bus is then free for another transmission (Figure 3).
Serial Interface
Serial Addressing
The MAX7310 operates as a slave that sends and receives data through a 2-wire interface. The interface uses a serial data line (SDA) and a serial clock line (SCL) to achieve bidirectional communication between master(s) and slave(s). A master, typically a microcontroller, initiates all data transfers to and from the MAX7310, and generates the SCL clock that synchronizes the data transfer (Figure 2). Each transmission consists of a start condition sent by a master, followed by the MAX7310 7-bit slave address plus an R/W bit, a register address byte, one or more data bytes, and finally a stop condition (Figure 3).
Bit Transfer
One data bit is transferred during each clock pulse. The data on SDA must remain stable while SCL is high (Figure 4).
Acknowledge
The acknowledge bit is a clocked 9th bit, which the recipient uses as a handshake receipt of each byte of data (Figure 5). Thus, each byte transferred effectively requires 9 bits. The master generates the 9th clock pulse, and the recipient pulls down SDA during the acknowledge clock pulse, such that the SDA line is stable low during the high period of the clock pulse. When the master is transmitting to the MAX7310, the MAX7310 generates the acknowledge bit since the MAX7310 is the recipient. When the MAX7310 is transmitting to the master, the master generates the acknowledge bit.
Start and Stop Conditions
Both SCL and SDA remain high when the interface is not busy. A master signals the beginning of a transmission with a start (S) condition by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a stop (P) condition by transitioning SDA from low to high while
Slave Address
The MAX7310 has a 7-bit-long slave address (Figure 6). The 8th bit following the 7-bit slave address is the R/W bit. Set this bit low for a write command and high for a read command.
SDA
tBUF tSU, DAT tLOW SCL tHD, DAT tSU, STA tHD, STA tSU, STO
tHIGH tHD, STA tR START CONDITION tF REPEATED START CONDITION STOP CONDITION START CONDITION
Figure 2. 2-Wire Serial Interface Timing Diagrams
SDA
SCL
S START CONDITION
P STOP CONDITION
Figure 3. Start and Stop Conditions 6 _______________________________________________________________________________________
2-Wire-Interfaced 8-Bit I/O Port Expander with Reset MAX7310
SDA
SCL DATA LINE STABLE; DATA VALID CHANGE OF DATA ALLOWED
Figure 4. Bit Transfer
START CONDITION SCL 1 2
CLOCK PULSE FOR ACKNOWLEDGMENT
8
9
SDA BY TRANSMITTER
S SDA BY RECEIVER
Figure 5. Acknowledge
FIXED
PROGRAMMABLE
SDA
0
A5
A4
A3
A2
A1
A0
R/W
ACK
MSB SCL
LSB
Figure 6. Slave Address
The first bits (MSBs) of the MAX7310 slave address are always zero. Slave address bits AD2, AD1, and AD0 choose 1 of 56 slave ID addresses (Table 7). Registers The register address byte is the first byte to follow the address byte during a read/write transmission. The reg-
ister address byte acts as a pointer to determine which register is written or read. The input port register is a read-only port. It reflects the incoming logic levels of the I/O ports, regardless of whether the pin is defined as an input or an output by the configuration register. Writes to the input port register are ignored.
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2-Wire-Interfaced 8-Bit I/O Port Expander with Reset
Table 1. Register Address
REGISTER ADDRESS (hex) 0x00 0x01 0x02 0x03 0x04 0xFF FUNCTION Input port register Output port register Polarity inversion register Configuration register Timeout register Reserved register PROTOCOL Read byte. Read/write byte. Read/write byte. Read/write byte. Read/write byte. Factory reserved. Do not write to this register.
Table 2. Register 0--Input Port Register
BIT I7 I6 I5 I4 I3 I2 I1 I0
The polarity inversion register enables polarity inversion of ports defined as inputs by the configuration register. Set the bit in the polarity inversion register (write with a 1) to invert the corresponding port pin's polarity. Clear the bit in the polarity inversion register (write with a zero) to retain the corresponding port pin's original polarity. The configuration register configures the directions of the ports. Set the bit in the configuration register to enable the corresponding port pin as an input with a high-impedance output driver. Clear the bit in the configuration register to enable the corresponding port pin as an output. Set bit T0 to enable the bus timeout function and low to disable the bus timeout function. Enabling the timeout feature resets the serial bus interface when SCL stops either high or low during a read or write access to the MAX7310. If either SCL or SDA is low for more than 30ms min and 60ms max after the start of a valid serial transfer, the interface resets itself. Resetting the serial bus interface sets up SDA as an input. The MAX7310 then waits for another start condition.
MAX7310
The output port register sets the outgoing logic levels of the I/O ports, defined as outputs by the configuration register. Reads from the output port register reflect the value that is in the flip-flop controlling the output selection, not the actual I/O value, which may differ if the output is overloaded.
Standby
The MAX7310 goes into standby when all pins are set to V+ or GND. Standby supply current is typically 1.7A.
Table 3. Register 1--Output Port Register
BIT Default O7 0 O6 0 O5 0 O4 0 O3 0 O2 0 O1 0 O0 0
Table 4. Register 2--Polarity Inversion Register
BIT Default I/O7 1 I/O6 1 I/O5 1 I/O4 1 I/O3 0 I/O2 0 I/O1 0 I/O0 0
Table 5. Register 3--Configuration Register
BIT Default I/O7 1 I/O6 1 I/O5 1 I/O4 1 I/O3 1 I/O2 1 I/O1 1 I/O0 1
Table 6. Register 4--Timeout Register
BIT Default T7 x T6 x T5 x T4 x T3 x T2 x T1 x T0 1
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2-Wire-Interfaced 8-Bit I/O Port Expander with Reset MAX7310
Table 7. MAX7310 Address Map
AD2 GND GND GND GND V+ V+ V+ V+ GND GND GND GND V+ V+ V+ V+ GND GND GND GND V+ V+ V+ V+ SCL SCL SCL SCL SDA SDA SDA SDA SCL SCL SCL SCL SDA SDA SDA SDA AD1 SCL SCL SDA SDA SCL SCL SDA SDA GND GND V+ V+ GND GND V+ V+ GND GND V+ V+ GND GND V+ V+ SCL SCL SDA SDA SCL SCL SDA SDA SCL SCL SDA SDA SCL SCL SDA SDA AD0 GND V+ GND V+ GND V+ GND V+ SCL SDA SCL SDA SCL SDA SCL SDA GND V+ GND V+ GND V+ GND V+ SCL SDA SCL SDA SCL SDA SCL SDA GND V+ GND V+ GND V+ GND V+ A6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
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2-Wire-Interfaced 8-Bit I/O Port Expander with Reset MAX7310
Table 7. MAX7310 Address Map (continued)
AD2 SCL SCL SCL SCL SDA SDA SDA SDA SCL SCL SCL SCL SDA SDA SDA SDA AD1 GND GND V+ V+ GND GND V+ V+ GND GND V+ V+ GND GND V+ V+ AD0 SCL SDA SCL SDA SCL SDA SCL SDA GND V+ GND V+ GND V+ GND V+ A6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Applications Information
Power-Supply Consideration
The MAX7310 operates from a supply voltage of 2.3V to 5.5V. Bypass the power supply to GND with a 0.047F capacitor as close to the device as possible. For the QFN version, connect the underside exposed pad to GND.
Chip Information
TRANSISTOR COUNT: 10,256 PROCESS: BiCMOS
10
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2-Wire-Interfaced 8-Bit I/O Port Expander with Reset MAX7310
DATA FROM SHIFT REGISTER
CONFIGURATION REGISTER D FF D Q FF CK Q ESD-PROTECTION DIODE GND INPUT PORT REGISTER D FF Q INPUT PORT REGISTER DATA Q OUTPUT PORT REGISTER DATA
DATA FROM SHIFT REGISTER
WRITE CONFIGURATION PULSE WRITE PULSE
CK
Q I/O0
OUTPUT PORT REGISTER
READ PULSE DATA FROM SHIFT REGISTER WRITE POLARITY PULSE
CK
Q
D FF CK
Q
POLARITY REGISTER DATA
Q
POLARITY INVERSION REGISTER
Figure 7. Simplified Schematic of I/O0
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11
2-Wire-Interfaced 8-Bit I/O Port Expander with Reset MAX7310
DATA FROM SHIFT REGISTER OUTPUT PORT REGISTER DATA V+
CONFIGURATION REGISTER D FF Q ESD-PROTECTION DIODE Q D FF CK Q ESD-PROTECTION DIODE OUTPUT PORT REGISTER INPUT PORT REGISTER D FF Q Q
DATA FROM SHIFT REGISTER
WRITE CONFIGURATION PULSE WRITE PULSE
CK
I/O1 TO I/O7
GND
INPUT PORT REGISTER DATA
READ PULSE DATA FROM SHIFT REGISTER WRITE POLARITY PULSE
CK
Q
D FF CK
Q
POLARITY REGISTER DATA
Q
POLARITY INVERSION REGISTER
Figure 8. Simplified Schematic of I/O1-I/O7
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2-Wire-Interfaced 8-Bit I/O Port Expander with Reset MAX7310
SCL 1 2 3 4 5 6 7 8 9 COMMAND BYTE A1 A0 0 A 0 0 0 0 0 0 0 1 A DATA TO PORT DATA 1 A P
SLAVE ADDRESS SDA S 0 A5 A4 A3 A2
START CONDITION WRITE TO PORT
R/W ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
DATA OUT FROM PORT tPV
DATA 1 VALID
Figure 9. Write to Output Port Register Through Write-Byte Protocol
SLAVE ADDRESS SDA S1 0 A5 A4 A3 A2 A1 A0 1 A
DATA FROM PORT DATA 1 A
DATA FROM PORT DATA 4 NA P
START CONDITION WRITE FROM PORT
R/W
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM MASTER
NO ACKNOWLEDGE FROM MASTER
STOP CONDITION
DATA INTO PORT tPH
DATA 2
DATA 3 tPS
DATA 4
NOTE 1: THIS FIGURE ASSUMES THE COMMAND HAS PREVIOUSLY BEEN PROGRAMMED WITH 0x00. NOTE 2: TRANSFER OF DATA CAN BE STOPPED AT ANY MOMENT BY A STOP CONDITION. WHEN THIS OCCURS, DATA PRESENT AT THE LAST ACKNOWLEDGED PHASE IS VALID (OUTPUT MODE). INPUT DATA IS LOST.
Figure 10. Read Input Port Register Through Receive-Byte Protocol
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2-Wire-Interfaced 8-Bit I/O Port Expander with Reset MAX7310
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
24L QFN THIN.EPS
PACKAGE OUTLINE 12, 16, 20, 24L THIN QFN, 4x4x0.8mm
21-0139
C
1
2
PACKAGE OUTLINE 12, 16, 20, 24L THIN QFN, 4x4x0.8mm
21-0139
C
2
2
14
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2-Wire-Interfaced 8-Bit I/O Port Expander with Reset
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
TSSOP4.40mm.EPS
MAX7310
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH
21-0055
E
1
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
QSOP.EPS

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